Embedded Hardware Structures for Efficient Volume and In-Field Diagnosis of Random Logic Circuits

A cost critical yet necessary step in high volume manufacturing of integrated circuits is test. Test is performed on every manufactured part not only to sort out defective parts, but also to monitor and calibrate the manufacturing process. Regarding the technology scaling of the last decades, this feedback to the manufacturing process is more and more becoming a necessity in order to achieve a satisfiable manufacturing yield.
For sorting out defective parts a pass/fail information from the test process is sufficient. However, for a valuable feedback, diagnostic information is required, i.e. information on the root causes of failures. While for sorting out defective parts, nowadays, cost efficient test schemes are available, the aggregation of diagnostic information is still inefficient and in some cases with the aforementioned test schemes even impossible.
This thesis presents test schemes which enable a cost efficient diagnosis during manufacturing test. By exploiting all capabilities of leading-edge diagnosis methods, an autonomous identification of relevant diagnostic information by the tested part itself is enabled. An according tool chain automates the optimal synthesis of the test schemes for any random logic circuit. The schemes can be varied in their degree of autonomy. With less autonomy they become cheaper in terms of on-chip area overhead, with full autonomy they have an insignificant overhead compared to state of the art schemes, and can be reused in the field. Thereby, they constitute the first autonomous test and diagnosis scheme for random logic circuits in literature. The schemes are experimentally evaluated. The results demonstrate that using the schemes for manufacturing test can reduce costs massively.