Hochberger, Christian; Koch, Andreas; Weinhardt, Markus (Ed.)

Fourth International Workshop on FPGAs for Software Programmers (FSP 2017)

September 7, 2017, Ghent, Belgium co-located with International Conference on Field Programmable Logic and Applications (FPL)

2017, 81 pages, Slimlinebox, CD-Rom
ISBN 978-3-8007-4443-5
Personal VDE Members are entitled to a 10% discount on this title

Content Foreword

The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken.

The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends. This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized target platforms. This will in particular put focus on the requirements of software developers and application engineers. In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware. Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development. In addition, the FSP Workshop shall facilitate collaboration of the different domains.

Topics of the FSP Workshop include, but are not limited to:
• High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
• Mapping approaches and tools for heterogeneous FPGAs
• Support of hard IP blocks such as embedded processors and memory interfaces
• Development environments for software engineers (automated tool flows, design frameworks and tools, tool interaction)
• FPGA virtualization (design for portability, resource sharing, hardware abstraction)
• Design automation technologies for multi-FPGA and heterogeneous systems
• Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility, reliability, or programmability
• Operating system services for FPGA resource management, reliability, security
• Target hardware design platforms (infrastructure, drivers, portable systems)
• Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
• Applications (e.g., embedded computing, signal processing, bio informatics, big data, database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc.
• Directions for collaborations (research proposals, networking, Horizon 2020)
Christian Hochberger (Proceedings Chair, Technische Universität Darmstadt, Germany) received his diploma in computer science and his doctorate in engineering from the Technische Universität Darmstadt in 1992 and 1998 respectively. Since 2012 he holds the chair for computer systems at the Technische Universität Darmstadt in the Electrical and Informatian Engineering department. Before that, he was full professor at the TU Dresden in the computer science department. His research is focused on reconfigurable HW architectures ranging from FPGA based SoCs to compute accelerators in the form of Coarse Grain Reconfigurable Arrays. He is a member of IEEE and GI and is an active reviewer for a number of conferences and journals.

Andreas Koch (Co-Chair), Technische Universität Darmstadt, Germany) received his diploma in informatics and his doctorate in engineering in 1992 and 1997, respectively, both from the Technical University Braunschweig (Germany). He then joined the University of California at Berkeley as a Post-Doctoral Scholar and returned to Braunschweig in 1999, continuing his research on hardware architectures and design tools. After his habilitation in 2005, Andreas Koch joined the Technische Universität Darmstadt (Germany) as Computer Science faculty, heading the newly founded Embedded Systems and Applications Group. His current research interests include hardware/software co-compilers, computer architecture and compute-intense embedded systems. He is a member of ACM, GI, IEEE, and a Principal Investigator at the Center for Advanced Security Research (CASED) in Darmstadt. He has led or participated in a number of national and international research projects on application-specific computer architectures and their programming tools.

Markus Weinhardt (Co-Chair, Osnabrück University of Applied Sciences, Germany) received his diploma in informatics and his doctorate in engineering in 1992 and 1997, respectively, both from the Technical University Karlsruhe (Germany). He is a member of the IEEE and holds a professorship for "Hardware and Software Systems for Information Processing" at Osnabrück UAS, Germany. His main research interests are high-level compilation methods for reconfigurable architectures (including FPGAs and Coarse-Grain Reconfigurable Arrays), reconfigurable and parallel processor architectures, and image processing. Markus has (co-)authored more than 30 conference papers, journal publications and book chapters and holds several patents. He currently serves on the program committees of several international conferences (FPL, ARC, ReConFig) and served as reviewer for several international journals (ACM TRETS, Hindawi IJRC, Optimization Letters).


1

A Case for Better Integration of Host and Target Compilation When Using OpenCL for FPGAs

Authors:
Lloyd, Taylor; Chikin, Artem; Ochoa, Erick; Ali, Karim; Nelson Amaral, Jose
2

PCIeHLS: an OpenCL HLS framework

Authors:
Vespera, Malte; Kocha, Dirk; Phama, Khoa
3

SOCAO: Source-to-Source OpenCL Compiler for Intel-Altera FPGAs

Authors:
Rohde, Johanna; Martinez-Peiro, Marcos; Gadea-Girones, Rafael
4

A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis

Authors:
Özkan, M. Akif; Reiche, Oliver; Hannig, Frank; Teich, Juergen
5

Accelerating Linux Bash Commands on FPGAs Using Partial Reconfiguration

Authors:
Horta, Edson; Shen, Xinzi; Pham, Khoa; Koch, Dirk
6
7

Spatial Memory Trace Prediction

Authors:
Gebara, Nadeen Yassir; Ienne, Paolo; Fleming, Kermin
8

C++ support for better hardware/software co-design in C# with SME

Authors:
Skovhede, Kenneth; Vinter, Brian
9

On the HLS Design of Bit-Level Operations and Custom Data Types

Authors:
Garcia Ordaz, Jose Raul; Koch, Dirk
10

Using GCC Analysis Techniques to Enable Parallel Memory Accesses in HLS

Authors:
Rohde, Johanna; Hochberger, Christian