Convergence Speed and Throughput of Analog Iterative Decoders for Low-Density Parity-Check (LDPC) Codes
Conference: TURBO - CODING - 2006 - 4th International Symposium on Turbo Codes & Related Topics; 6th International ITG-Conference on Source and Channel Coding
04/03/2006 - 04/07/2006 at Munich, Germany
Proceedings: TURBO - CODING - 2006
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Hemati, Saied; Banihashemi, Amir H. (Broadband Communications and Wireless Systems (BCWS) Centre, Department of Systems and Computer Engineering, Carleton University, Ottawa, ON, K1S 5B6, Canada)
This paper is concerned with the implementation of iterative decoding algorithms in analog VLSI. We study the convergence speed and throughput of analog decoders for low-density parity-check (LDPC) codes, and show that they depend on the code, the decoding algorithm, and the average time constant of the analog circuit interconnections. They however are not a function of the variance of the time constants and change only slightly with signal to noise ratio. The analysis presented here can be used for selecting suitable codes and decoding algorithms for analog decoding. Furthermore, it can be used to estimate the throughput of an analog decoder, if the average time constant of the analog circuit is known.