Low-complexity LDPCC decoder based on layered decoding and MIN-SUM approximation
Conference: TURBO - CODING - 2006 - 4th International Symposium on Turbo Codes & Related Topics; 6th International ITG-Conference on Source and Channel Coding
04/03/2006 - 04/07/2006 at Munich, Germany
Proceedings: TURBO - CODING - 2006
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Valle, Stefano (STMicroelectronics srl, Italy)
LDPCC are becoming a valid alternative to Turbo Codes. They have been incorporated into the specifications of several real systems, but often the resulting decoders compose a significant fraction of the digital transceivers. As a consequence, a lot of research is currently focused on their simplification. The bulk of an LDPCC decoder is comprised of memories and check-node processing unit(s). The present work introduces a memory efficient decoding algorithm that jointly exploits the simplification of check-node processing by means of the MIN-SUM approximation, and a recently introduced scheduling of the Sum-Product Algorithm (SPA), namely layered decoding, that shows a twice faster convergence of the iterative process. The performances of the proposed algorithm are comparable with the SPA, but ~70% less memory is required. Further potential advantages in real implementations are briefly discussed.