A High-Speed Analog Trellis Decoder with Low-Energy Consumption

Conference: TURBO - CODING - 2006 - 4th International Symposium on Turbo Codes & Related Topics; 6th International ITG-Conference on Source and Channel Coding
04/03/2006 - 04/07/2006 at Munich, Germany

Proceedings: TURBO - CODING - 2006

Pages: 6Language: englishTyp: PDF

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Gioulekas, Fotios; Birbas, Michael; Bilionis, George; Birbas, Alexios (Department of Electrical and Computer Engineering, University of Patras, Campus of Rion, 26500, Patras, Greece)

Recent analog implementations of channel decoders, which are used to decode powerful error correcting schemes, have shown promising results for lower-power consumption and higher-speed than their digital counterparts. This work presents the implementation of an analog trellis decoder that takes advantage of the high-speed features of SiGe HBTs. Its fast error correcting capability of 20nsec outperforms relevant analog decoders and digital decoders, as well. The simulated total throughput of the decoder, including the delay time introduced by the input and the output interfaces, is 55.55 Mbit/s for a total latency of 180nsec. The energy consumption per decoding bit is 8.57nJ/b for a total power consumption of 476mW. The design is based on AMS 0.35micrometer SiGe BiCMOS process.