A Low Complexity and Programmable Encoder Architecture of the LDPC Codes for DVB-S2
Conference: TURBO - CODING - 2006 - 4th International Symposium on Turbo Codes & Related Topics; 6th International ITG-Conference on Source and Channel Coding
04/03/2006 - 04/07/2006 at Munich, Germany
Proceedings: TURBO - CODING - 2006
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Yokokawa, Takashi; Nakane, Misa; Kan, Makiko (Sony Corporation, Gate City Osaki West Tower Osaki East Tec., 1-11-1 Osaki Shinagawa-ku, Tokyo, 141-0032, Japan)
We propose a low complexity and programmable encoder architecture of the LDPC codes for DVB-S2 standard, where 21 variations of LDPC codes are defined. The proposed LDPC encoder takes advantage of the features of the codes, that is quasi cyclic codes and irregular repeat-accumulator codes. The key issue for realizing low complexity is a quasi-cyclic encoder using RAMs instead of shift registers. We implemented a programmable encoder circuit which is applicable to all LDPC codes defined in DVB-S2 standard, achieving easy operation.