Inclusion of Critical Layout Interconnect Parasitics at Schematic Entry Using Partial Layout Flow Approach

Abstract:
Design flows need to become more interconnect-centric, as Integrated Circuits (ICs) are scaled into nanometer dimensions and operate at giga-hertz frequencies. To determine IC performance and predict accurate design behavior, it is important to model in minimum the most critical interconnect- and bus structures. This should be done not only efficiently, but also early in the design process – if possible during schematic entry. For RF or fast digital designs, an RLCK-extraction including substrate mesh might be required to get reliable simulation results. This paper describes a flow to identify, model and optimize interconnects at schematic entry, prior to the knowledge of the full layout topology. For validation, simulation results are compared with corresponding results of the fully extracted layout. With this flow, the time taken to model critical interconnect structures is short, compared to the standard full chip methodology, commonly used in today’s back-end flows. Nevertheless, a significant increase in accuracy can be observed, compared to schematic simulations, using ideal wires.