Circuit Design-for-Yield (DFY) for a 110dB Op-Amp for Automotive and Sensor Applications
Conference: ANALOG '06 - 9. ITG/GMM-Fachtagung
09/27/2006 - 09/29/2006 at Dresden, Germany
Proceedings: ANALOG '06
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Rooch, Karl-Heinz; Sobe, Udo (ZMD Zentrum Mikroelektronik Dresden AG, Grenzstraße 28, 01109 Dresden)
Pronath, Michael (MunEDA GmbH, Stefan-George-Ring 29, 81929 München)
The scope of this paper is to show how tools for analog design automation can assist a modern topology design on the example of a high gain operational transconductance amplifier (OTA). A design method is presented that involves a combination of topology improvement and yield optimization by utilizing the tools zmdAnalyser and WiCkeD. We used the possibility to interactively analyze and size the circuit design for an exhaustive analysis of a hierarchical circuit as well as to understand limitations of different circuit topologies. In this way, we achieved a final topology with a high simulated parametric yield. The OTA is designed for ZMD’s 0.6m standard CMOS technology. The design contains about 130 active devices and measures 300x300micrometer2. Taking into account process variation, mismatch, the large automotive temperature range and a supply voltage range of 5V ±10%, a dc gain of more than 110dB and a unity-gain frequency greater than 50MHz for a 9pF load were achieved. The settling time is less than 100ns with an accuracy finer than 0.01%. The consumed supply current is about 2.5mA.