A Multimode Shared RF Low-Power Receiver Front-End Architecture for Satellite Based Navigation in 90 nm CMOS

Abstract:
Next generation wireless communication devices demand complex integrated analog and mixedsignal RF circuitry. Typical multimode architectures use parallel paths for simultaneous reception of different applications which leads to high power consumption and large silicon area. In contrast to this, the softwaredefined radio approach uses more complex reconfigurable blocks, but a simultaneous use of different communication services is not possible. In order to overcome the dilemma, this work presents an exemplary receiver for satellite based navigation, that simultaneously covers the three positioning systems GPS (USA), Galileo (Europe) and Glonass (Russia). The benefits of simultaneous use of these systems are increased localization accuracy and a high robustness to interferers resulting in better quality of service at the cost of only a negligible overhead in terms of power consumption and die area. A top-down design approach with system level simulations as well as analog circuit simulation results for critical blocks and a full chip verification are presented. The proposed receiver is designed in an industrial 90nm standard CMOS technology and is operated from a supply voltage of 1Volt only.