Analysis of Parasitic Effects in Large Analog Circuits
Conference: ANALOG '08 - Entwicklung von Analogschaltungen mit CAE-Methoden - Schwerpunkt: Constraint-basierte Entwurfsmethoden - 10. GMM/ITG-Fachtagung
04/02/2008 - 04/04/2008 at Siegen, Germany
Proceedings: ANALOG '08
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Sobe, Udo; Graupner, Achim (ZMD Zentrum Mikroelektronik Dresden AG, Grenzstraße, 01109 Dresden)
Post layout simulation is state of the art to consider parasitic effects in designed circuits. It is usually expensive for the designer to find the performance killer(s) in large designs with help of post layout simulation. The paper demonstrates methodologies and tools to analyze systematically the influence of parasitics. Todays common flows are discussed, compared and a improved way is presented. It bases on filtering extracted parasitic devices out of a netlist. The parasitic extraction step and post layout analysis is decoupled. This allows the implementation in automated procedures. Design methodology and results realized by the authors will be presented for two circuits for automotive and industry applications. The first example shows how netlist filter technique can be applied to improve manual parasitic analysis. About 10 simulation runs were used to find perturbing parasitic effects of a circuit with about 1850 extracted parasitic capacities. The second example shows a semi-automated method. Totally 45 simulation runs were started via script to isolate perturbing parasitic effects of a circuit with 1600 parasitic capacities. Such low count of simulation runs can not be reached by common analysis like the classical sensitivity analysis.