A Behavioral PLL Model with Timing Jitter due to White and Flicker Noise Sources

Conference: ANALOG '08 - Entwicklung von Analogschaltungen mit CAE-Methoden - Schwerpunkt: Constraint-basierte Entwurfsmethoden - 10. GMM/ITG-Fachtagung
04/02/2008 - 04/04/2008 at Siegen, Germany

Proceedings: ANALOG '08

Pages: 6Language: englishTyp: PDF

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Höppner, S.; Henker, S.; Schüffny, R. (Technische Universität Dresden, Fakultät für Elektrotechnik und Informationstechnik, Professur für Hochparallele VLSI-Systeme und Neuromikroelektronik)

This paper presents a time domain behavioral phase-locked loop model that includes jitter due to white and flicker phase noise sources. The jitter is concentrated in two model blocks which include time domain noise generators for colored noise. The jitter behavior is described by a total number of four parameters. A simple analytical parameter extraction method is presented, that allows to find model parameters from phase noise simulations or measurements. The proposed modeling method is validated by simulations and measurements of a 2GHz PLL in 180nm CMOS technology.