Issues and Options for Planar Packaging of High-Voltage SiC Diodes
Conference: CIPS 2008 - 5th International Conference on Integrated Power Electronics Systems
03/11/2008 - 03/13/2008 at Nuremberg, Germany
Proceedings: CIPS 2008
Pages: 7Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Xu, Jing; Ngo, Khai D. T.; Calata, Jess; Wyk, J. D. van (Center for Power Electronics System (CPES), Virginia Polytechnic Institute and State University, US)
Wyk, J. D. van (Dept. of Electrical and Electronic Engineering Science, University of Johannesburg, South Africa)
As the voltage rating of power semiconductors rises, so must the voltage rating of device packages. The planar packaging scheme with Embedded Power technology is a good candidate for device packaging because of its reduced parasitics and better thermal performance. This paper analyzes the issues of this planar technology in the case of a 10 kV SiC diode package using a device simulator, MEDICI. Given the proposed structure, the geometry and material properties that could influence the electric field distribution are studied. Two options for the planar package are proposed and simulated.