Yield Optimization to Gain Reliable and Area Efficient Data-Converters using Nonideal Nanoscale Processes

Abstract:
Behavioural modeling and yield optimization of resistor string based (potentiometer) Digital-to-Analog-Converters (DACs) is presented to improve its reliability and area efficiency with focus on nonideal nanoscale CMOS processes, which suffer from large device tolerances. By arranging raw unit devices in a compound way the overall accuracy of these compound devices can be increased significantly, depending on the number of used unit devices, which is known as the statistical averaging principle. The behavioural model of the potentiometer DAC topology includes all relevant realistic performance degradation parameters. The optimization potential in terms of yield is analyzed taking systematic and statistical properties of the DAC topology into account. Two different 4096-step DACs using 65nm and 180nm CMOS process have been fabricated and evaluated. Measurement results show outstanding accuracy performance and excellent matching between measured and simulated circuit performance using the behavioural model. Guidelines for proper and efficient resistor string based DAC-Design are given.