Mask parameter variation in the context of the overall variation budget of an advanced logic wafer Fab
Conference: EMLC 2009 - 25th European Mask and Lithography Conference
01/12/2009 - 01/15/2009 at Dresden, Germany
Proceedings: EMLC 2009
Pages: 13Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Seltmann, Rolf; Burbach, Gert; Parge, Anne; Busch, Jens; Hertzsch, Tino; Poock, Andre; Weisbuch, Francois; Holfeld, Andre (AMD Fab36 LLC & Co. KG, Wilschdorfer Landstrasse 101, D-01069 Dresden, Germany)
Within our paper we are going to discuss the variation within the patterning process in the context of the overall electrical parameter variation in an advanced logic Fab. The evaluation is based on both the variation of ring oscillators that are distributed across the chip as well as on local variation of matched transistor pairs. Starting with a view back to the 130nm technology, we will show how things and requirements changed over time. In particular we focus on the gate layer where we do a detailed ACLV-comparison from the 130nm technology node down to today’s 45nm node. Within the patterning variation we keep special attention on the mask performance. Within that section, we do a detailed wafermask correlation analysis. Additionally to the low-MEEF gate layer we show the importance of the mask CDperformance for a typical high MEEF-layer. Finally, we discuss the mask contribution to the overall overlay error for the most critical contact to gate overlay. In all of the cases, we will show that the mask performance is not the limiter within today’s most advanced technology, as long as we get access to a world class mask shop.