High speed (>100 Gbps) key components for a scalable optical data link, to be implemented in future maskless lithography applications
Conference: EMLC 2009 - 25th European Mask and Lithography Conference
01/12/2009 - 01/15/2009 at Dresden, Germany
Proceedings: EMLC 2009
Pages: 8Language: englishTyp: PDF
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Authors:
Paraskevopoulos, A.; Voss, S.-H.; Talmi, M.; Walf, G. (Fraunhofer-Institute for Telecommunications, Heinrich-Hertz-Institut, Einsteinufer 37, 10587 Berlin, Germany)
Abstract:
Maskless lithography based on electron beam parallelization requires well adapted data links, capable of transmitting the corresponding data volume at rates up to the Tbps domain. In this paper we focus on two key components, the highspeed data buffer unit and the integrated optical receiver, which are part of a scalable (24 – 140 Gbps) optical data link. The high-speed buffer design architecture enables the transmission of skew-compensated parallel data in the range of 50 Gbps. The 45-channel low-noise integrated optical receiver chip based on BiCMOS 0.6 micron technology is capable of an overall transmission capacity of 140 Gbps.