Reduction of Network Models of Parasitic Coupling Effects in Mixed-Signal VLSI Circuits

Abstract:
In this paper a method for the efficient reduction network models of parasitic couplings in modern integrated circuits is presented. The focus lies on the disturbance of the analog part generated by the digital switching currents. The parasitic effects are modeled by large RLC networks and current sources for the digital switching currents. Based on the determined behavior of the digital modules an efficient description of these networks is proposed, which allows for a higher model reduction than standard methods. The proposed method enables a fast and efficient simulation of the parasitic effects. Additionally an extension of the reduction method to elements, which incorporate some supply voltage dependence to model the internal currents more precisely than independent current sources, is presented.