Learning Optimal Synthesis of Voltage Regulator Circuits through Comparative Study in PSPICE
Conference: ISTET 2009 - VXV International Symposium on Theoretical Engineering
06/22/2009 - 06/24/2009 at Lübeck, Germany
Proceedings: ISTET 2009
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Marinova, Galia; Dimitrov, Dimitar (Technical University – Sofia)
The paper presents a Learning Environment for Optimal Synthesis of Voltage Regulator Circuits (LEOS-VRC) using PSPICE simulator. LEOS-VRC can help teaching and self education in design of voltage regulator circuits. It’s suitable for students in electronics, electrotechniques, telecommunications and computer-science engineering as well as doctoral students and designers of power supply circuits.