Learning Environment for Design and Verification of Communication Circuits Realized on FPGA
Conference: ISTET 2009 - VXV International Symposium on Theoretical Engineering
06/22/2009 - 06/24/2009 at Lübeck, Germany
Proceedings: ISTET 2009
Pages: 3Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Marinova, Galia (Technical University – Sofia)
The paper presents a Learning Environment for design and verification of communication circuits realized on FPGA, which is developed and applied in the laboratory for Computer-aided design in the Telecommunications faculty in Technical University (TU) – Sofia. IP blocks of digital signal processing functions and communication systems like modems and cryptoprocessors can be designed and tested in the environment.