FPGA based Prototyping of Next Generation Forward Error Correction
Conference: ECOC 2009 - 35th European Conference on Optical Communication
09/20/2009 - 09/24/2009 at Vienna, Austria
Proceedings: ECOC 2009
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Mizuochi, T.; Konishi, Y.; Miyata, Y.; Inoue, T.; Onohara, K.; Kametani, S.; Sugihara, T.; Kubo, K.; Kobayashi, T.; Yoshida, H.; Ichikawa, T. (Mitsubishi Electric Corporation, Japan)
The concatenation of LDPC and RS codes has been demonstrated using a real-time FPGA prototype. A net coding gain of 9.0dB for 31.3-Gb/s was achieved with 20.5% redundancy for an input BER of 10-2.