43Gb/s CP-QPSK Realtime Receiver Demonstrator based on FPGAs and Block-Processing
Conference: ECOC 2009 - 35th European Conference on Optical Communication
09/20/2009 - 09/24/2009 at Vienna, Austria
Proceedings: ECOC 2009
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Geyer, Jonas C.; Schmauss, Bernhard (Chair for High Frequency Technology, University of Erlangen, Germany)
Fludger, Chris R. S.; Duthel, Thomas; Presslein, Paul; Schulien, Christoph (CoreOptics GmbH, Nuremberg, Germany)
We present measurement results of an FPGA-based 43Gb/s Realtime Coherent Receiver Demonstrator. Due to limitations we use block-aggregation and process 1/32 of the input data stream. We show back-to-back performance and chromatic dispersion tolerance.