Design for reliability of analog circuits in nanometer CMOS technology
Conference: Zuverlässigkeit und Entwurf - 3. GMM/GI/ITG-Fachtagung
09/21/2009 - 09/23/2009 at Stuttgart, Germany
Proceedings: Zuverlässigkeit und Entwurf
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Gielen, Georges; Maricau, Elie; Wit, Pieter De (ESAT-MICAS, Department of Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium)
Reliability is becoming one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems relate to increased external interference such as caused by crosstalk and EMI, as well as due to technology-related degradation mechanisms like NBTI, causing time-dependent circuit performance degradation. Variability only makes these things more severe. This creates a need for innovative design techniques and design tools that help designers coping with these reliability and variability problems. This invited overview paper first describes design tools for the efficient analysis and identification of reliability problems in analog circuits. Next, it presents novel circuit design techniques to mitigate these problems. They can be used either at design time before tapeout or through run-time circuit adaption and reconfiguration after fabrication. This will be illustrated with some design examples.