An interleaving scheme for efficient binary LDPC coded higher-order modulation
Conference: SCC'10 - 8th International ITG Conference on Source and Channel Coding
01/18/2010 - 01/21/2010 at Siegen, Germany
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Nowak, Stefan; Kays, Rüdiger (Communication Technology Institute, Department of Electrical Engineering and Information Technology, Dortmund University of Technology, Dortmund, Germany)
This paper addresses bit-interleaving for low-density parity-check (LDPC) coded modulation in AWGN and Rayleigh channels. We present an interleaving scheme that accounts for the different bit reliabilities inherent to higher-order modulation and the unequal error protection (UEP) properties of irregular LDPC codes. Therefore, we analyze the UEP properties and introduce a metric indicating the influence of a bit node on the decoding process. Based on this and earlier results from related work we derive an intuitive interleaving scheme that improves the performance of LDPC coded modulation. The bit error rate is reduced with respect to the required Eb/N0 as well as the mean number of iterations performed by the decoder. The performance evaluation is based on the rate one-half and three-quarter LDPC codes with a block length of 1944 bits according to IEEE 802.11n and 256-QAM with Gray mapping. The simulation results show up to 0.5 dB modulation/coding gain for a Rayleigh channel. Furthermore, for certain signal-to-noise ratios the mean number of iterations for decoding is reduced by up to ten iterations. Hence, applying a dedicated interleaver to LDPC coded modulation systems increases the overall efficiency.