Inductive Parasitics in Power Semiconductor Modules subject to Multi-Objective Optimisation

Abstract:
Capacitive and inductive parasitics that exist in every electrically conducting structure are inseparably associated with the geometry. Especially in power electronics the geometry also is defined through thermal aspects which can approximately be analytically investigated when static results of behaviour are satisfying. Single-objective optimisation is not satisfying as long as knowledge on its impact on other parasitics is unpredictable. Eventually a combined multi-objective optimisation process is desired. For this purpose evolutionary algorithms empower an optimisation process that incrementally keeps the best compromise solutions. Fitness functions are defined through all optimisation objectives - e.g. minimisation of all electrical and thermal parasitics. PEEC (partial element equivalent circuit) method is suitable to extract the electrical parasitics as lumped parameters for an adequately subdivided current path of the electrically conducting layer. Because this method is based on volumetric decomposition it empowers a method to change the layout within optimisation process without high recalculation effort. Approaches for methodical application of aforementioned processes are studied.