Operating System Processor Scheduler Design for Future Chip Multiprocessor
Conference: ARCS 2010 - 23th International Conference on Architecture of Computing Systems
02/22/2010 - 02/23/2010 at Hannover, Germany
Proceedings: ARCS 2010
Pages: 7Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Xu, Thomas Canhao; Yin, Alexander Wei; Liljeberg, Pasi; Tenhunen, Hannu (University of Turku, Department of Information Technology, 20520 Turku, Finland)
Today’s Chip Multiprocessor (CMP) designs are mainly based on the shared-bus communication architecture. However, as the scale of CMPs increase, this architecture suffers from high communication delay and power inefficiency. Therefore, network-on-chip (NoC) based architecture is proposed as a promising technique for future very large scale CMPs. The operating system (OS) scheduling is one of the most important design issues for CMP systems. In this paper, limitations of state-of-the-art OS scheduler are discussed, with Sun Solaris used as a case study. The contribution of this paper lies in the on-chip data traffic calculation of runtime applications. By evaluating FFT and SPECjbb as benchmarks, it is shown that the Solaris scheduler does not provide the optimal communication scheme and thus suffers from the network latency and overall performance degradation. We define a model for NoC-based CMP, based on which a scheduling algorithm is proposed to minimize communication latencies. The weights of memory access and inter process communication in scheduling are analyzed. A protocol for OS implementation of the algorithm has been proposed in this paper. Our analysis and experiment results provide a guideline for the designs of future multicore schedulers.