A Hybrid Transport/Control Operation Triggered Architecture
Conference: ARCS 2010 - 23th International Conference on Architecture of Computing Systems
02/22/2010 - 02/23/2010 at Hannover, Germany
Proceedings: ARCS 2010
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Moser, Nico; Hauser, Stefan; Gremzow, Carsten (TU Berlin, Department of Computer Engineering and Microelectronics, 10587 Berlin, Germany)
We present an approach to a scalable and extensible processor architecture with inherent parallelism named synZEN. One aim was to create a synthesizable application specific processor which can be mapped to an FPGA. Besides architectural features like the interconnection network for flexible data transport and synZEN units with communication managing interface we give an overview of the programming model, show basic operation design and depict assembler notations to program these architecture. The paper closes with a brief toolchain overview and some synthesis results that support our design decisions.