Modeling Separate Memory Spaces in Native Co-simulation with SystemC for Design Space Exploration
Conference: ARCS 2010 - 23th International Conference on Architecture of Computing Systems
02/22/2010 - 02/23/2010 at Hannover, Germany
Proceedings: ARCS 2010
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Posadas, Hector; Villar, Eugenio (University of Cantabria, Santander, Spain)
High-level co-simulation has become critical in recent years as a solution to check and evaluate large systems. Languages as SystemC provide the required base to simulate SW tasks and HW components together in a flexible way at different abstraction levels. To effectively perform the simulations at different levels, additional extensions to these languages are required. For high-level native co-simulations, several works has been centered in providing new capabilities for SW modeling to Systemc. Tasks schedulers, time estimation and annotation techniques and HW/SW interfacing capabilities have been developed for that purpose. However, for simulating mUlti-process systems there are still important limitations. As standard SystemC simulations are based on a single executable, techniques for modeling the memory space separation are needed to integrate different processes in the same simulation. Integrating several processes containing global variables or functions with the same names, or duplicating components in SystemC is not directly possible. This paper proposes a technique to integrate independent codes using the same names for global variables and functions in a single SystemC simulation without manual recoding. The technique achieves automatic separation of visibility scopes to allow combining codes without name duplication errors.