A Scheduling Approach for Efficient Utilization of Hardware-Driven Frequency Scaling

Conference: ARCS 2010 - 23th International Conference on Architecture of Computing Systems
02/22/2010 - 02/23/2010 at Hannover, Germany

Proceedings: ARCS 2010

Pages: 10Language: englishTyp: PDF

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Schönherr, Jan H.; Richling, Jan (Communication and Operating Systems, Technische Universität Berlin, Germany)
Mühl, Gero (Architecture of Application Systems, University of Rostock, Germany)
Werner, Matthias (Operating Systems Group, Chemnitz University of Technology, Germany)

Multi-core processors are able to deliver excellent throughput. However, if a multi-core processor is not fully utilized, the achieved performance is below that of a processor of the same technology with less cores: To stay within the same power envelope, the power used by additional transistors of a multi-core processor must be compensated by reducing the cores’ operating voltage and frequency. Recently, processors have been equipped with mechanisms considerably reducing the power consumption of cores which are either idle or not fully utilized. This raises the opportunity to increase clock frequency in phases of low utilization again as long as no limit is exceeded. This idea is exploited by Intel’s Turbo Boost Technology in its recent processors. However, current operating systems are not aware of this mechanism as the decision of increasing clock frequency is done entirely in hardware inside the processor. In this paper, we show that the ignorance of this technology by operating systems can have a negative impact on both, performance as well as energy consumption. We also give a first approach to tackle this problem by separation in time which shows good results. It exploits knowledge about hardware-driven frequency scaling to achieve (i) a better performance for important tasks accepting an increased energy consumption while (ii) minimizing energy consumed by unimportant tasks.