An opamp array test structure for stress test measurements
Conference: Zuverlässigkeit und Entwurf - 4. GMM/GI/ITG-Fachtagung
09/13/2010 - 09/15/2010 at Wildbad Kreuth, Germany
Proceedings: Zuverlässigkeit und Entwurf
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
John, Bibin; Hafkemeyer, Kristian M.; Krautschneider, Wolfgang H. (Institute of Nanoelectronics, Hamburg University of Technology (TUHH), Hamburg, Germany)
This paper is about setting up of an opamp array test structure for investigating the degradation of differential amplifier circuit performance and variation of its individual transistor parameters in a stress test. In an analog circuit implemented using transistors with ultra-thin gate dielectric oxide, the increased gate leakage current results in the increased chances of transistor dielectric breakdown and effects significantly the circuit performance. Differential amplifiers with transistors having tox=2.2 nm are designed for applying voltage and temperature stresses. Transmission gates and other logic circuitry transistors with oxide thickness 6.5 nm are used to stress the differential amplifier circuit and to address individual transistors in the differential amplifier circuit. An array of 16 differential amplifiers with transmission gates are implemented for stress test measurements.