Noise Properties of Asymmetrically Recessed InP-based HEMTs for Low-noise Amplifiers
Conference: IPRM 2011 - 23th International Conference on Indium Phosphide and Related Materials
05/22/2011 - 05/26/2011 at Berlin, Germany
Proceedings: IPRM 2011
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Takahashi, T.; Sato, M.; Makiyama, K.; Nakasha, Y.; Hirose, T.; Hara, N. (Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan)
Low-noise amplifiers (LNAs) need appropriate transistors to operate with high performance; i.e., the first-stage amplifier in the LNAs requires low-noise property, in particular, and the succeeding stages require high gain with high breakdown voltage. In this study, we proposed InP-base HEMTs with an asymmetric gate-recess structure for high-gain amplifiers with a low noise figure. A gate-drain spacing (Lrd) of around 100 nm in the gate-recess region was suitable for first-stage amplifiers. Furthermore, a large Lrd of 250 nm was suitable for obtaining high gain in the succeeding stages.