Reduction of source parasitic capacitance in vertical InGaAs MISFET
Conference: IPRM 2011 - 23th International Conference on Indium Phosphide and Related Materials
05/22/2011 - 05/26/2011 at Berlin, Germany
Proceedings: IPRM 2011
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Matsumoto, Yutaka; Saito, Hisashi; Miyamoto, Yasuyuki (Tokyo Institute of Technology, O-okayama, Meguro, Tokyo, Japan)
We previously reported that a vertical InGaAs MISFET with an electron launcher, undoped channel to prevent electron scattering, and 15-nm-wide mesa achieved a high current density of 7 MA/cm2. However, the reported structure was designed only for DC operation, as it had a large parasitic capacitance between the gate electrode and source. Here we report on the impact of this parasitic capacitance on high-speed operation and the effectiveness of a BCB insulating layer in mitigating the capacitance. In measurements on a test element group, insertion of a BCB layer reduced the parasitic capacitance from 27.6 pF/cm to 1.68 pF/cm, and transistor operation with an inserted BCB layer was confirmed.