ExtraTime: A Framework for Exploration of Clock and Power Gating for BTI and HCI Aging Mitigation
Conference: Zuverlässigkeit und Entwurf - 5. GI/GMM/ITG-Fachtagung
09/27/2011 - 09/29/2011 at Hamburg-Harburg, Deutschland
Proceedings: Zuverlässigkeit und Entwurf
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Oboril, Fabian; Tahoori, Mehdi B. (Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany)
Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are two major causes for transistor aging at nano-scale, leading to slower devices, more failures during runtime, and ultimately reduced lifetime. Typically these issues are handled by adding extra guardbands to the design, i. e. overdesign, which results in lower clock frequencies and hence, performance losses. Alternatively, efficient aging mitigation techniques can be used to relax such guardbands. In this paper we explore various clock and power gating techniques for BTI and HCI aging mitigation at microarchitecture-level for superscalar processors. This is done with the help of our aging-aware microarchitectural framework 'ExtraTime', which includes a cycle-accurate performance simulator together with microarchitectural models to estimate power consumption, temperature, and particularly aging. The simulation results show that using an aging-optimized combination of clock and power gating, aging (delay) of the execution units of a 32 nm superscalar microprocessor due to BTI can be reduced by 30 % while aging due to HCI is mitigated by 70 %. This is achieved with only 2 % reduction in performance (IPC). This gives one the possibility to either extend the lifetime by 3 times, or reduce the guardbands.