Stacking-based Input Reordering for NBTI Aging Reduction
Conference: Zuverlässigkeit und Entwurf - 5. GI/GMM/ITG-Fachtagung
09/27/2011 - 09/29/2011 at Hamburg-Harburg, Deutschland
Proceedings: Zuverlässigkeit und Entwurf
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Kiamehr, Saman; Firouzi, Farshad; Tahoori, Mehdi B. (Karlsruhe Institute of Technology, Karlsruhe, Germany)
Transistor aging due to Negative Bias Temperature Instability (NBTI) is becoming a major reliability challenge for the lifetime operation of VLSI circuits fabricated using nanoscale technology nodes. Since NBTI exponentially related to the PMOS transistor threshold voltage as well as gate-source voltage, transistor stacking has a strong effect on NBTI. In this paper, we propose a stacking based input pin reordering technique to reduce the impact of NBTI on the logic gates during active mode operation. According to the results, our proposed approach increases the operational lifetime of VLSI chips by 11.9%, in average, while it has negligible effects on performance, area, and power compared to the original cell input ordering.