Variation of Propagation Delay and Power Dissipation in CMOS Due To Input Pattern and Technology Scaling
Conference: Zuverlässigkeit und Entwurf - 5. GI/GMM/ITG-Fachtagung
09/27/2011 - 09/29/2011 at Hamburg-Harburg, Deutschland
Proceedings: Zuverlässigkeit und Entwurf
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Al-Eryani, Jidan; Sattler, Sebastian (Chair of Reliable Circuits and Systems, University of Erlangen-Nuremberg, Erlangen, Germany)
The propagation delay and power dissipation are two decisive circuit parameters. In this article, the dependency of these parameters in static CMOS logic due to input pattern and their transitions across different technology scales are reviewed using SPICE circuit simulations. The logic gates used to exemplify these variations are an inverter, a NAND, and a NOR. The scale technologies used are 0.35micrometer, 0.25micrometer, 0.13micrometer, and 90nm.