Adaptive Digital Signal Processor based on Floating Point Units for Rapid Prototyping of Electronic Units in Adaptronic Systems
Conference: MikroSystemTechnik - KONGRESS 2011
10/10/2011 - 10/12/2011 at Darmstadt, Deutschland
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Samman, Faizal Arya; Glesner, Manfred (Technische Universität Darmstadt, Germany)
Samman, Faizal Arya (LOEWE-Zentrum AdRIA, Fraunhofer Institut LBF, Darmstadt, Germany)
Glesner, Manfred (ForschungsgruppeMikroelektronische Systeme, Merckstr. 25, 64283 Darmstadt, Germany)
A hardware design of adaptive digital signal processor (DSP) using floating-point arithmetic units for rapid prototyping of electronic units in adaptronic systems is presented in this paper. Two main components in the arithmetic units are 32-bit (single-precision) adder and multiplier. A filter cell is designed as a modular unit to implement an FIR and IIR filter. The filter cell has been synthesized by using 180-nm CMOS standard-cell technology, where the total logic cell area of the cell is 0.314 mm2. The cell can be clocked at maximum of 350 MHz with post-synthesis estimated dynamic power of 112 mW. In order to minimize the logic cell area, a sequential architecture of the filter is proposed. Reliability issue on the embedded DSP for adaptronics is also briefly discussed in this paper.