Bridging the Gap between Simulink and Analog Design Environments Using HDL Code Generation
Conference: ANALOG '11 - 12. GMM/ITG-Fachtagung
11/07/2011 - 11/09/2011 at Erlangen, Deutschland
Proceedings: ANALOG '11
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Mauderer, Andreas; Oetjens, Jan-Hendrik (Robert Bosch GmbH, AE/EIM3, Tuebinger Strasse 123, 72762 Reutlingen, Germany)
Rosenstiel, Wolfgang (University of Tuebingen, Department of Computer Engineering, Sand 13, 72074 Tuebingen, Germany)
In common design flows for mixed-signal ASICs, system-level models are used as executable specifications. Based on these specifications, analog components are directly implemented on device-level. This step constitutes a large leap of abstraction. In this contribution, we address this aspect by showing and discussing an approach for automated transition from analog components of Simulink models representing heterogeneous systems to discrete-time, continuous-value VHDL and Verilog behavioral models. The generated behavioral models are integrated into analog design environments and serve as reference for implementation. Furthermore, the approach is used during the verification process by adapting the system-level model to implementation characteristics and by repeated generation of the behavioral model. An evaluation of the presented design flow will be shown by applying the flow to an automotive hardware design.