Digital mismatch calibration of charge redistribution SAR ADCs

Conference: ANALOG '11 - 12. GMM/ITG-Fachtagung
11/07/2011 - 11/09/2011 at Erlangen, Deutschland

Proceedings: ANALOG '11

Pages: 4Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Voelker, Matthias; Visakh, Jithin; Hauer, Johann (Fraunhofer Institute for Integrated Circuits IIS, Erlangen, Germany)

A low power, small area 12 bit 100 kS/s successive approximation charge redistribution ADC in 150 nm CMOS technology is presented using 43 fF metal-insulator-metal capacitors. Capacitor mismatch which limits the circuit performance and yield is analysed. A mismatch estimation and correction scheme is explained in detail which is able to compensate for mismatch variation of more than ±3 times of the standard deviation. The estimation algorithm is optimized to use only a zero voltage input signal for parameter extraction. In order to achieve INL performance better than ±1 LSB an additional bit of resolution is employed for calibration without additional analog circuitry.