A flexible hardware architecture for real-time airborne Wavenumber Domain SAR processing
Conference: EUSAR 2012 - 9th European Conference on Synthetic Aperture Radar
04/23/2012 - 04/26/2012 at Nuremberg, Germany
Proceedings: EUSAR 2012
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Pfitzner, M.; Cholewa, F.; Pirsch, P.; Blume, H. (Institute of Microelectronic Systems, Leibniz University Hannover, Germany)
This paper presents the design of a compact real-time SAR hardware architecture for small unmanned aerial vehicles (UAVs). The architecture is flexible for a variety of SAR algorithms whereby the focus of this paper is on the wavenumber domain (ω-k) algorithm. Characteristics of the RISC/FPGA based hardware architecture are real-time processing for sensor data rates of 300 Mbit/s with image dimensions of 8k x 4k pixel, implemented on a 233 x 160 mm printed circuit board with a total power dissipation below 15 W.