Reducing Parasitic Electrical Parameters with a Planar Interconnection Packaging Structure
Conference: CIPS 2012 - 7th International Conference on Integrated Power Electronics Systems
03/06/2012 - 03/08/2012 at Nuremberg, Germany
Proceedings: CIPS 2012
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Liang, Zhenxian; Ning, Puqi; Wang, Fred; Marlino, Laura (Oak Ridge National Laboratory, Oak Ridge, TN, USA)
A novel packaging structure for medium power modules featuring power semiconductor switches sandwiched between two symmetric substrates that fulfill electrical conduction and insulation functions is presented. The power switches in a popular phase leg electrical topology are orientated in a face up/face down configuration. Large bonding areas between dies and substrates combined with a compact busbar interface allow this packaging technology to offer dramatic improvements in electrical conversion efficiency and electromagnetic interference containment.