Integrated Anti-Short-Circuit Safety Circuit in CMOS SOI for Normally-On JFET
Conference: CIPS 2012 - 7th International Conference on Integrated Power Electronics Systems
03/06/2012 - 03/08/2012 at Nuremberg, Germany
Proceedings: CIPS 2012
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Falahi, Khalil El; Dubois, Fabien; Bergogne, Dominique; Risaletto, Damien; Allard, Bruno (Université de Lyon, Ampère, CNRS UMR 5005, Lyon, France)
The SiC JFET is a commercially available device either as a normally-on or a normally-off configuration. The latter cascode configuration incorporates a Si MOSFET that prevents the usage of the device in harsh environment, i.e. ambient temperature greater than 200deg C. Besides the acceptance of the normally-on native device is linked to an industrial and validated solution to avoid the inherent short-circuit when operated in an inverter leg. The short-circuit appears when the inverter is powered-on and the SiC JFET drivers are not in a position to apply an off-state condition to the power switches. There is then a need for a safety circuit that provides the off-state condition to the power switches in the shortest period of time. Such a safety circuit is detailed and fabricated as an integrated circuit in SOI CMOS technology.