Consideration of Electrical Parasitics in Conjunction with Thermal Behaviour of Power Semiconductor Components
Conference: CIPS 2012 - 7th International Conference on Integrated Power Electronics Systems
03/06/2012 - 03/08/2012 at Nuremberg, Germany
Proceedings: CIPS 2012
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Förster, Stefan; Lindemann, Andreas (Otto-von-Guericke-University Magdeburg, Institute of Electric Power Systems, Chair for Power Electronics, Universitätsplatz 2, 39106 Magdeburg, Germany)
Capacitive and inductive parasitics of every electrically conducting structure are inseparably associated with geometry. Especially in power electronics thermal optimisation along with minimisation of occupied circuit layer area has the demand for a thick metallisation to improve heat spreading. Electrical optimisation by means of minimisation of formation of parasitics instead aims on flat structures. Multi-objective optimisation aims on best compromise solutions. The paper considers a half-bridge configuration of transistors and diodes to investigate aforementioned parasitics by use of simulation. Validation of the results by measurements provide the possibility to use dispersed parameters of simulation results for optimisation purposes.