Quality evaluation for silver sintering layers in power electronic modules

Conference: CIPS 2012 - 7th International Conference on Integrated Power Electronics Systems
03/06/2012 - 03/08/2012 at Nuremberg, Germany

Proceedings: CIPS 2012

Pages: 6Language: englishTyp: PDF

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Rudzki, Jacek; Osterwald, Frank (Danfoss Silicon Power GmbH, Schleswig, Germany)
Jensen, Lars (University of Applied Sciences, Kiel, Germany)
Poech, Max; Schmidt, Lothar (Fraunhofer ISIT, Itzehoe, Germany)

This publication presents a quality evaluation method based on thermal impedance test (Zth) to detect delaminations in the sintered power modules. For this purpose an emulated delamination has been used as a test standard. Common test methods such a SAM and X-Ray microscopy are also presented and their suitability for testing of sinter layers is discussed. First results for Lock-In thermography for detection of defects in sinter layers are presented. The Zth test method is based on the measurement of the junction temperature Tj of the semiconductor device after a short current pulse. The duration of this current pulse has to be constant for all devices to provide a defined thermal power. A delaminated layer beneath the silicon die corrupts the heat dissipation path and leads to increased junction temperature. The deviation in Tj provides information about the condition of the joining layer between the silicon die and the substrate. Measurement results of the Zth tests are verified by using FEM thermal simulation, SAM and Lock-In thermography. A thermal model to predict the influence of delaminations in the sintered layer on the junction temperature is presented as well.