Smart Power Gate Array for Cost-Aware Single-Chip Integration of Industrial Applications
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Zhang, Yipin; Scherjon, Cor; Burghartz, Joachim N. (Institute for Microelectronics Stuttgart (IMS-CHIPS), D-70569 Stuttgart, Germany)
The Smart Power Gate Array, a novel mixed-signal and smart-power capable ASIC platform is presented. Offering low nonrecurring engineering (NRE) costs of low-voltage mixedsignal capable gate array technology and flexibly configurable smart power functionalities, the new smart power gate array provides a cost- and performance optimized integration platform for industrial applications. Based on the demonstration chip fabricated in a 0.8micrometer high-voltage, bipolar CMOS DMOS, silicon on insulator (HV BCD SOI) process, concept and construction of the smart power gate array are described in detail and the applicability of the platform is successfully demonstrated.