Digital Fractional and Asynchronous Oversampling for High Speed Δ-Σ Modulators

Abstract:
The concept, application and implementation of a digital oversampling topology suitable for fractional and asyn- chronous oversampling are presented in this work. The presented concept enables a larger variety of oversampling factors. Thus, the maximum possible oversampling frequency can be increased. Therefore, the signal-to-noise ratio of a subsequent δ-σ modulator can be increased. Transmitter frontends using ?? modulation for an increased effective resolution are the focused application for this concept. In these topologies oversampling factors are limited by aspects as the carrier frequency or the fixed sampling rate of the baseband digital signal processor. Cir- cumventing these limits can increased significant the performance of a such a transmitter frontend. The presented topology enables fractional and asynchronous oversampling based on the input and output clock signal. By generating intermediate clock signals timing violations are avoided. Thus, data samples can cross from a slower to a faster clock domain. This oversampling circuit adds only four register stages. Hence, the complexity is only marginally increased. Aliases of the oversampled signal are suppress by an flexible anti-alias filter. Furthermore, the presented filter allows wideband alias suppression to enable wideband signals like long term evolution (LTE). Therefore, the resulting signals are usable for δ-σ modulation. The presented concept is evaluated by system simulations and verified timing simulations on synthesised circuits in a current 65nm CMOS process.