16-Bit Clocked Adiabatic Logic (CAL) Leading One Detector for a Logarithmic Signal Processor
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Yemiscioglu, Gurtac; Lee, Peter (School of Engineering and Digital Arts, University of Kent, Canterbury, Kent CT2 7NT)
This paper describes the architecture of a Leading- One Detector (LOD) and its implementation using Clocked Adiabatic Logic (CAL). This modular circuit has been designed for use in a 16-bit logarithmic signal processor but can easily be adapted for longer or shorter word lengths. The circuit can also be used as the first stage in a floating-point converter. It has been designed using an AMS 0.35 µm CMOS process and consumes an area of 0.02 mm2. Spice simulations have shown that the circuit can operate at frequencies up to 250 MHz and energy calculation have indicated 20.38 pJ power consumption at the maximum operating frequency.