A novel CAM-based Information Detection Hardware System on FPGA
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Le, Duc-Hung; Pham, Cong-Kha (The University of Electro-Communications, Tokyo, Japan)
Inoue, Katsumi (Advanced Original Technologies, Chiba, Japan)
A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of searching and matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-matched results concurrently. The system operates based on the CAMs for pattern matching in parallel manner to output multiple addresses of multi-matched results. Based on the parallel multimatching operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The detection time of the multimatched results is achieved at 60ns. Thus increases the matching performance of the information detection system which uses this method as the core system. Keywords — FPGA, Information Detection Hardware System, Content Addressable Memory, Random Access Memory, parallel operation, multiple match.