Towards Synthetic Benchmarks Generator for CAD Tool Evaluation

Abstract:
In the process of designing prototyping CAD tools for system on chip, industrial need usually huge benchmark designs to test and evaluate their tools. However, observing the limits of existing and available bench- marks, it is necessary to develop and provide large suites of synthetic benchmarks with more specific characteristics. In this paper, we present a benchmark generator providing various sets of architectures. The generation includes also the creation of the executable code of the application which will be executed in the hardware architecture. In the experimental results, we show that our generator is able to generate various sets of synthetic benchmarks with several millions of gates. Those sets includes hierarchical, heterogeneous and asynchronous circuits.