Digital Polar Transmitter Architecture suitable for multi-core SoC Integration in 65 nm CMOS Technology
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDF
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Authors:
Li Puma, Giuseppe; Getta, Klaus; Ishak Loza, Andreas; Feltgen, Michael; Wiedenhaus, Marco; Christ, Volker (Intel Mobile Communications, Duisburg, Germany)
Marsili, Stefano; Reindl, Christian; Thaller, Edwin (Infineon Villach, Austria)
Dai, Yanzhong (Intel Mobile Communications, Xian, China)
Caterini, Marc (Intel Mobile Communications, Sophia Antipolis, France)
Schoenauer, Tim (Intel Mobile Communications, Munich, Germany)
van Waasen, Stefan (Forschungszentrum Jülich GmbH, Germany)
Heinen, Stefan (RWTH-Aachen, Germany)
Abstract:
We propose a digital polar transmitter architecture for integration in multi-core SoC’s in deepsubmicron CMOS technology. The novel transmitter addresses wireless connectivity standards with the objective to realize a highly digital architecture at a low current consumption fulfilling coexistence requirements with cellular and global positing systems (GPS) on the same device. To achieve a high power efficiency the transmitter power amplifier (PA) is built to operate from a switched 1.8 V DCDC supply. The prototype is verified in a 65-nm CMOS process demonstrating compliant differential error vector magnitude (DEVM) figures for all channels and spectral modulation mask performance. Index Terms — Polar transmitter, Polar modulator, SoC