A Flexible 5 ps Bin-Width Timing Core for Next Generation High-Energy-Physics Time-to-Digital Converter Applications
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Perktold, Lukas (Graz University of Technology, Rechbauerstr. 12, 8010 Graz, Austria)
Christiansen, Jørgen (CERN, 1211 Geneva 23, Switzerland)
A new flexible low-power timing core for high time resolution time-to-digital converter (TDC) applications is presented. The chosen architecture allows a high number of channels using only one instance of the timing core to be efficiently implemented. It uses a multi-stage conversion scheme employing a delay-locked-loop (DLL) in its first stage and a power efficient passive interpolation scheme in its second stage, to achieve bin-widths as low as 5 ps. A delay-cell, using an additional zero in its signal path, to achieve delays shorter than 20 ps in a 130nm technology is described. The architecture, important design trade-offs and simulation results are presented.