System design of a 24 GHz phased-array front-end for low-power applications
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Wang, Ban (Ecole Polytechnique F´ed´erale de Lausanne, Electronics and Signal Processing Laboratory, Neuchˆatel, Switzerland)
Tasselli, Gabriele; Botteron, Cyril; Farine, Pierre-André (Ecole Polytechnique Fédérale de Lausanne, Electronics and Signal Processing Laboratory, Neuchâtel, Switzerland)
This paper deals with the design of a 4-channel phased-array receiver Front-End (FE) architecture working at 24 GHz. Targeting low power applications such as radar sensors and medium bit-rate transceivers, a local oscillator shifting architecture is proposed and designed. Some fundamental blocks have been developed in 90 nm Complementary Metal-Oxide- Semiconductor (CMOS) technology, namely a low noise amplifier, a vector modulation phase shifter and a quadrature voltage controlled oscillator. Their post-layout simulated data have been used inside the Advanced Design System software environment, together with state-of-the-art models for the mixer and combiner, in order to evaluate the layout effects on the whole FE per- formance. The proposed phased-array receiver system provides continuous beam steering operation, a noise figure of 3.5 dB and a power consumption of less than 200 mW.