Real-Time Error Correction of High Speed Time-Interleaved Analog-to-Digital Converters with State of the Art FPGA Technology
Conference: PRIME 2012 - 8th Conference on Ph.D. Research in Microelectronics & Electronics
06/12/2012 - 06/15/2012 at Aachen, Germany
Proceedings: PRIME 2012
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Ferenci, Damir; Mauch, Simon; Digel, Johannes; Berroth, Manfred (Institute of Electrical and Optical Communications Engineering, University of Stuttgart, 70569 Stuttgart, Germany)
High speed time-interleaved analog-to-digital converters (TIADCs) suffer from gain, offset and timing errors wich reduce their effective resolution. By a posterior digital error correction this errors can be corrected. To achieve this, known error models are applied to the converters. Error estimation and error correction approaches are derived from these models. A realization of a digital real-time posterior error estimation and error correction is implemented in VHDL for a 3 to 6 bit analogto- digital converter with a sampling rate up to 24GS/s.